Audio signal delay apparatus and method

ABSTRACT

An apparatus for delaying an audio signal in conformance with the format of the audio signal. An input device is receptive to an audio signal having one of a plurality of formats. A processing device coupled to the input device is operable to provide a delay in the audio signal corresponding to the format of the audio signal. The delayed audio signal is output through an output device. An audio format detection circuit is operable to detect the number of edge transitions within a known period in a processed audio signal and thereby determine the format of the audio signal by comparing a detected edge transition count to model data representative of the plurality of formats.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.09/478,122 filed Jan. 5, 2000, which application is hereby incorporatedby reference.

FIELD OF THE INVENTION

The present disclosure relates to video and audio circuits and moreparticularly to circuits that provide a delay in an audio signal andfurther to circuits that synchronize audio signals with video signals.

BACKGROUND OF THE INVENTION

Household video technology began decades ago with an analogstation-transmitted video signal, a roof top antenna, and a threechannel black and white television set in a living room. Since then,video technology has experienced rapid growth due to advances inmicroprocessor, communications, and digital signal processingtechnology. In addition to the standard television, the video market hasexpanded to include video cassette recorders (VCR), multiple providersof satellite television, digital cable, video on-demand cable, digitaltelevision, hi-definition television, overhead projection television,home movie theaters, camcorder video units and many other video options.As technology continues to develop, the list of video options availableto the consumer will continue to grow as well.

The vast video market has led to an expansion of video formats currentlyin use by these different products. In fact, some products have morethan one video format. For example, digital television transmission hasbeen approved and is in operation in the United States. The standard fordigital television includes 18 new video formats.

The increasing number of video products and corresponding video formatshas created a problem of compatibility between products. In order toexperience video from one format in another format, the video streammust be processed and transformed into the desired format. For example,to view video formatted according to the interlaced scanning scheme usedin analog television standards on a computer display that usesprogressive scanning, a format transformation must be performed.

Before this transformation occurs, a video signal and its correspondingaudio signal are synchronized to temporally correspond to each other. Asa result of the format transformation, the required signal processingintroduces an undesirable delay in the video stream, causing the videoand audio streams to be unsynchronized. That is, as a result of thetransformation, conversations and sound effects in the video may notmatch a speaker's mouth or events as they occur. Furthermore, as signalsare processed through more than one device, this delay becomes greaterand more noticeable to the viewer. The transformation processingtherefore requires that the video and audio signal be re-synchronized toeliminate the undesirable mismatching of the video and audio signals.

A delay introduced in the audio signal provided to synchronize the audioand video signal is dependent upon the format of the video andcorresponding audio signal. As discussed above, a number of formats areused for digital video signals. These formats accommodate variable audiosampling rates and sample sizes. Furthermore, digital audio signals arecommonly transported from one processing device to another within anaudio/video processing product using a number of serial transmissionschemes. These schemes use various methods to mark the start of a sampleor determine left from right in a stereo pair. One example of such aserial audio stream is a standard known as I²S. As such, different typesof digital audio signals require a different delay in order to beproperly re-synchronized to their corresponding processed video signal.

Circuits that adjust an audio signal to account for the delay requiredby video signal processing are well known in the art. However, pastsolutions of the prior art consist of circuits that provide a delay inthe audio signal only for video transformed from one specific format toanother. In order to provide the appropriate audio delay for differentvideo format transformations using the solutions in the prior art,several circuits are required as shown in FIG. 1. This solution requiresadditional hardware and adds expense to the consumer. Furthermore, inmany practical cases, the processing device which converts the videoformats may have no information regarding which audio format is in use,thus providing an improper delay or otherwise impairing thesynchronization process.

What is needed is an apparatus that can determine the digital serialaudio format in use, and then automatically delay the serial digitalaudio stream to synchronize the audio and video streams.

SUMMARY OF THE INVENTION

A disclosed embodiment solves the problem of providing a delay in adigital serial audio signal corresponding to the particular format ofaudio signal while minimizing the required hardware. The disclosedembodiment determines the audio sample size and sample rate by comparingthe frequency of the serial audio clock to a known reference frequency.It also uses the serial clock to sample the serial audio data signals.It then stores the stream of data in a memory which is configured as acircular buffer having a write pointer and a read pointer. The addressspace between the pointers corresponds to a particular time delay in thedata, for example, as the differences in the address increases, so doesthe delay in reading the data relative to when it was written. Theserial audio clock is then used again to output the serial audio datasignals such that a delay in the serial digital audio data stream isachieved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the prior art providing a delay formultiple formats of digital audio signals.

FIG. 2 is a block diagram of the audio delay apparatus.

FIG. 3 is a block diagram of the audio delay circuit.

FIG. 4 is a flow chart of the operation of the audio delay circuit.

FIG. 5 is a block diagram of the audio format detection circuit.

FIG. 6 is a flow chart of the operation of the audio format detectionand write address generation circuit.

DETAILED DESCRIPTION

As shown in FIG. 2, AN audio delay circuit generally designated 95includes an input device 700, a processing device 800, and an outputdevice 900. The input device 700 is receptive to an incoming audiosignal 701. As is known in the art the audio signal may be composed ofnumerous separate component signals. In the present embodiment, theaudio signal includes a serial data signal, a frame synchronizationsignal, and a clock signal. The frame synchronization signal may havemany formats and variations and is referred to by different namesdepending upon the product provider. This disclosure uses the term“frame synchronization signal” as a broad term meant to include signalssuch as left and right stereo signals, single pulse signals, data packetstart signals, and any other signal that marks the beginning of a packetof data in the audio signal. As is known in the art there are many termsused to label this type of signal and they are all incorporated as theterm frame synchronization signal is used in the present disclosure.

As shown in FIG. 3, the audio delay circuit 95 further includes a FIFOregister 10, an audio format detection circuit 20, a memory controllercircuit 30, a memory chip 40, a write address generator 50, a readaddress generator 60, a control state machine 70, and an audio datainput FIFO 80.

With the reference of FIG. 4, the circuit flow generally designated 1000generally includes an operation 100 in which data signals are input intothe FIFO register 10, an operation 200 in which data signals are storedin a memory circuit, an operation 300 in which the audio signal formatis detected, an operation 400 in which the audio signal delay isimplemented according to the audio signal's detected format, anoperation 500 in which the data signals are retrieved from memory, andan operation 600 in which the data signals are output with the properdelay implemented.

The operation of the audio delay circuit 95 as shown in FIG. 3 will nowbe described. Circuit operation begins with the Audio Data Input FIFO 10receiving the data signal clock and accompanying data signals. In apreferred embodiment, the data signals received are a serial data signalthrough data line 2, a frame synchronization signal through data line 4,and an audio clock signal through data line 6. Packets of data or framesfrom the data signals accompanying the audio clock signal are loadedinto the FIFO register 10. The size of FIFO register 10 is determined bythe requirements of the memory system and the highest data flow rate tobe accommodated and is generally unrelated to any specific digitalserial audio format. The FIFO register 10 performs serial to parallelconversion of the digital serial audio data and provides temporarystorage of the data until a memory write cycle is requested. When FIFOregister 10 is full, the FIFO register 10 sends a FIFO full signal tothe control state machine 70 through FIFO full data line 14.

Upon receiving the FIFO full signal, the control state machine 70 sendsa write request to the memory controller 30 through read/write requestdata line 72. Upon receiving this request, the memory controller 30 putsthe request in a queue (not shown) and when other memory transactionsare complete, the memory controller 30 sends a signal to the input FIFOregister 10 which causes the FIFO register 10 to drive its contents intothe memory data bus 42 and into memory chip 40 under control of thememory controller 30 using control and address signals 44.

The format detection process will now be described. The format of theaudio signal is detected by the audio format detection circuit 20 shownin FIG. 3. The audio format detection circuit 20 is depicted in moredetail in FIG. 5 and its operation is shown in the flow chart of FIG. 6.As shown in FIG. 5, the circuit 20 includes a divide-by-constant-counter210, which in the preferred embodiment has a constant of 16, clocked bythe audio shift clock (SCK) 8, a circuit 220 to synchronize thedivide-by-constant signal to a 27 MHz clocking domain, a counter 230clocked by 27 MHz, a latch 240 to store the previous state of thecounter 230, a comparing circuit 250 containing comparators 251 through258 which compare the stored count to predetermined values, a lookupmemory circuit 260, a write address latch 270, and a comparator 280.

With the reference of FIG. 6, the format detection circuit flowgenerally designated 300 generally includes an operation 310 in whichthe frequency of the audio shift clock is divided by a constant which inthe preferred embodiment is equal to 16 to create a SCK/16 signal, anoperation 320 in which the SCK/16 and 27 MHz clock are synchronized andedge detection occurs, an operation 330 in which the SCK/16 clears acounter and enables a latch to store the previous count, an operation340 in which the latched count is compared to constants, the result ofthe comparison used to select a Write Address, an operation 350 in whicha write address is latched, an operation 360 in which the current andlast Write Address are compared, an operation 380 in which no action isrequired if the last and current Write Address are equal, and anoperation 390 in which the Read Address Pointer is initialized and thecurrent Write Address is loaded into the Write Address Pointer.

The audio format detection circuit 20 receives the audio clock signal(SCK) through data line 8 and a reference clock signal through data line21. The SCK input clocks a 4 bit counter 210, which generates a timingsignal on data line 212 whose frequency is equal to SCK/16. This signalis sent through a synchronization and edge detection circuit 220, whereit is synchronized to the 27 MHz clock domain. The output of thesynchronizer 220 is a pulse on data line 214 whose frequency isnominally equal to SCK/16 and whose pulse width is equal to one periodof the 27 MHz clock. This pulse becomes a master timing signal. Thefollowing events occur once per period of this master timing signal.

The timing pulse clears a counter 230 which is clocked by 27 MHz. Thepulse also enables a latch 240 which stores the previous state of thecounter 230. The latch 240 now contains a binary number corresponding tothe number of cycles of the 27 MHz clock that occurred in the periodSCK/16.

Comparators 251 through 258 compare the contents of the latch 240 toeight constant values which correspond to various SCK frequencies. Theresults of the comparisons are used to select one of eight predeterminedWrite Address values which is captured in latch 270 such that the WriteAddress calculated in the previous period is compared to the WriteAddress calculated in the current period by the comparator 280.

If the Previous and Current Write Address values are equal, then thefrequency of the SCK has not changed and no further action is required.However, if the Previous and Current Write Addresses are not equal, thenthe SCK frequency has changed, and the memory Read and Write Pointersmust be initialized. The Read Address pointer is initialized with aconstant, and the Write Address pointer is initialized with the CurrentWrite Address calculated as described above. It will be apparent to oneskilled in the art that the operations described thus far may beaccomplished in a variety of ways, including but not limited toinitializing the Write Address pointer with a constant and initializingthe Read Address with a constant correlating to the detected format ofthe audio signal.

The delay for the audio signal is implemented by configuring a memoryregister (not shown) within the memory controller 30 corresponding tothe detected format of the sampled audio clock signal. As describedabove, each constant value within the comparator circuit 250 referencedabove corresponds to an offset value. This offset value is used toconfigure an address pointer that then configures the memory register.The memory register, configured by the address pointer corresponding tothe detected format, forms the delay required by the particular audioformat. The memory register is defined with a first parameter and asecond parameter. In one embodiment, the memory register is a buffer(not shown), the first parameter is a write address pointer and secondparameter is a read address pointer. The write address offsetinformation is provided by the audio format detection circuit 20 throughdata line 22 to the write address generator circuit 50.

Next, the memory controller 30 configures a write address pointer and aread address pointer. Information for these pointers is provided fromthe write address generator circuit 50 through data line 52 and the readaddress generator circuit 60 through data line 62. When the memorycontroller 30 receives the write address generator information, itresizes the buffer according to the configured write address and theread address pointers. The memory controller 30 then implements thedelay corresponding to the resized buffer.

The memory controller 30 sends a control signal on data line 44 to thememory chip 40 to send the stored data signal and frame synchronizationsignal through the memory data bus 42. The memory controller 30 thenreads the signals sent over the data bus 42. If the audio data inputFIFO 80 is presently empty, a FIFO empty signal is sent from the FIFOregister 80 to the control state machine 70 through data line 82. Inresponse to this signal, the control state machine 70 sends a readrequest signal through data line 72 to the memory controller 30. Uponreceiving this request, the memory controller 30 puts the request in aqueue (not shown), completes other memory transactions, and finallysends a signal to the memory chip 40 using data line 44 which causesdata to be read from the memory chip 40 and written to the input FIFO 80under control of the memory controller 30. The input FIFO 80 thenperforms a parallel to serial conversion and sends its contents tooutputs through data lines 84, 86 and 88 under control of the SerialAudio Clock (SCK).

In use, the disclosed circuit 90 provides for a delay in the audiosignal corresponding to the particular format of audio signal whileminimizing the required hardware. The disclosed embodiment determinesthe audio sample size and sample rate by comparing the frequency of theserial audio clock to a known reference frequency. It also uses theserial clock to sample the serial audio data signals. It then stores thestream of data in a memory which is configured as a circular bufferhaving a write pointer and a read pointer. The serial audio clock isthen used again to output the serial audio data signals such that adelay in the serial digital audio data stream is achieved.

Having thus described illustrative embodiments of the invention, it willbe apparent that various alterations, modifications and improvementswill readily occur to those skilled in the art. Such obviousalterations, modifications and improvements, though not expresslydescribed above, are nonetheless intended to be implied and are withinthe spirit and scope of the invention. Accordingly, the foregoingdiscussion is intended to be illustrative only, and not limiting; theinvention is limited and defined only by the following claims andequivalents thereto.

1. An apparatus for delaying an audio signal comprising: an input devicereceptive to an audio signal having one of a plurality of formats; aprocessing device coupled to the input device, the processing deviceconfigured for providing a delay in the audio signal corresponding tothe format of the audio signal; and an output device coupled to theprocessing device, the output device configured to output the audiosignal with the delay corresponding to the format of the audio signal.2. The apparatus as claimed in claim 1, wherein the audio signal furthercomprises a serial audio clock signal and a plurality of accompanyingsignals.
 3. The apparatus as claimed in claim 2, wherein theaccompanying signals further comprises a data signal and a framesynchronization signal.
 4. The apparatus as claimed in claim 2, whereinthe accompanying signals are loaded into a register.
 5. The apparatus asclaimed in claim 4, wherein the register is a FIFO register.
 6. Theapparatus as claimed in claim 4, wherein the accompanying signals arestored in a memory device.
 7. The apparatus as claimed in claim 6,wherein the memory device further comprises a memory controller and amemory chip.
 8. The apparatus as claimed in claim 1, wherein theprocessing device further comprises an audio format detection deviceoperable to detect the format of the audio signal.
 9. The apparatus asclaimed in claim 8, wherein the audio format detection device isoperable to detect a number of edge transitions in the serial audioclock signal and provide a corresponding detected count.
 10. Theapparatus as claimed in claim 9, wherein the audio format detectiondevice further comprises a plurality of model data, wherein each modeldata represents one of the plurality of audio signal formats and acorresponding one of a plurality of delay data, wherein the detectedcount is compared to the model data, the audio format detection deviceoperable to provide the delay data representing the model data that isequal to the detected count.
 11. The apparatus as claimed in claim 10,wherein the processed clock signal is synchronized to a reference clock.12. The apparatus as claimed in claim 8, wherein the audio formatdetection device is operable to provide a processed clock signal bydividing the serial audio clock signal by a constant.
 13. The apparatusaccording to claim 12, wherein the processing device is operable tocompare a new delay data to an old delay data, the processing deviceoperable to reconfigure a buffer if the new delay data is not equal tothe old delay data.
 14. The apparatus as claimed in claim 10, whereinthe detected count is compared to the model data by a plurality ofcomparators.
 15. The apparatus as claimed in claim 10, wherein theprovided delay data is a first offset value, the processing deviceoperable to resize a write address pointer with the offset value. 16.The apparatus as claimed in claim 10, wherein the provided delay data isa second offset value, the processing device operable to resize a readaddress pointer with the offset value.
 17. The apparatus as claimed inclaim 10, wherein the processing device further comprises a memory unitto provide the delay corresponding to the delay data.
 18. The apparatusas claimed in claim 15, wherein the processing device further comprisesa first parameter and a second parameter, the first parameter configuredaccording to the provided delay data.
 19. The apparatus as claimed inclaim 18, wherein the first parameter is a write address parameter, thesecond parameter is a read address parameter, and the memory unit is abuffer.
 20. A method for delaying an audio signal comprising the stepsof: receiving an audio signal having one of a plurality of formats;processing the audio signal to provide a delay corresponding to theformat of the received signal; and providing the audio signal with thedelay corresponding to the format of the signal.
 21. The method of claim22, wherein the audio signal further comprises a serial audio clocksignal and accompanying signals.
 22. The method of claim 21, wherein thestep of processing the audio signal further comprises the step ofproviding a processed serial audio clock signal, the processed serialaudio clock signal provided by dividing the serial audio clock signal bya constant.
 23. The method of claim 21, wherein the accompanying signalsfurther comprise a frame synchronization signal and a data signal. 24.The method of claim 21, wherein the step of processing the audio signalfurther comprises the step of storing the accompanying signals in amemory device.
 25. The method of claim 24, wherein the memory devicefurther comprises a memory chip and a memory controller.
 26. The methodof claim 22, wherein the step of processing audio signal furthercomprises the step of detecting the format of the audio signal:
 27. Themethod of claim 26, wherein the step of detecting the format of theaudio signal further comprises the steps of detecting the number of edgetransitions in the processed serial audio clock signal and providing adetected count.
 28. The method of claim 27, wherein the step ofdetecting the format of the audio signal further comprises the steps ofproviding a plurality of model data, wherein each model data correspondsto a serial audio clock signal format, providing a plurality of delaydata, wherein each delay data corresponds to a model data, comparing thedetected count to the plurality of model data and providing the delaydata corresponding to the model data equal to the detected count. 29.The method of claim 28, further comprising the step of comparing thedetected count to the plurality of model data using comparator circuits.30. The method of claim 28, wherein the detected count further comprisesthe number of edge transitions in the processed serial audio clocksignal within a period, and wherein the plurality of model data includethe number of edge transitions present in each processed serial audioclock signal format in the period.
 31. The method of claim 30, whereinthe step of processing the audio signal further comprises the step ofproviding a memory register having a first parameter and a secondparameter, the memory register configured to provide a delay.
 32. Themethod of claim 31, wherein the step of providing a memory registerfurther comprises the step of providing an offset, the offsetcorresponding to the model data equal to the detected count and resizingthe memory register by providing the offset for the first parameter. 33.The method of claim 32, wherein the first parameter is a write addresspointer, the second parameter is a read address pointer, and the memoryregister is a buffer.
 34. The method of claim 33, wherein the firstparameter is a read address pointer, the second parameter is a writeaddress pointer, and the memory register is a buffer.
 35. The apparatusas claimed in claim 1 further comprising an output device, coupled tothe processing device, to output the audio signal with the delaycorresponding to the format of the audio signal.